1. Field of Invention
The present invention relates to integrated circuit packaging, and more particularly to multiple die packaging.
2. Related Art
Semiconductor die or chip packages are used to protect the semiconductor device (e.g., an integrated circuit chip) and allow the chip to be electrically connected to external circuitry. The chip typically has a surface containing active circuit elements that can be accessed via conductors on the chip, such as bonding pads. The chip can be packaged using numerous packaging techniques, as is known in the art. The package can then be placed into a printed circuit board (PCB) to access the circuitry on the IC chip.
As the complexity of applications increases, a greater number of chips are needed on the PCB to implement the necessary functions. Conventional methods to increase the number of chips without increasing the package size is to stack multiple chips on the package, such as disclosed in U.S. Pat. No. 5,012,323 to Farnworth, U.S. Pat. No. 5,291,061 to Ball, U.S. Pat. No. 5,347,429 to Kohno et al., U.S. Pat. No. 5,780,925 to Cipolla et al., U.S. Pat. No. 5,793,108 to Nakanishi et al., and U.S. Pat. No. 5,898,220 to Ball. Although these disclose two or more stacked die each electrically connected to leads on the package or lead frame, none disclose the ability to connect the die together without connection to the external package leads, which limits the interconnection capability of signals between die, such as the wire bond fan-out of the package.
In order to increase signal routing capability, previous solutions included using higher cost laminate-based packages. Thus, it is desirable to have a stacked multiple-die package with high signal routing capability between die without the costs associated with laminate-based packages.
In the present invention, a method and structure are provided that allow multiple stacked die to be connected through internal conductive traces in the lead frame or package for high signal routing capability between die.
According to the present invention, electrically isolated signal traces within the paddle area are created for die-to-die signal interconnection and held together using lead lock tape. These signal traces are completely internal to the package and not connected to the external leads. Die are then stacked, either over each other or on both sides of the paddle area, and interconnected via the internal traces. A bond wire is connected from a bond pad of a first die to an internal trace. Another bond wire is connected from a bond pad of a second die to the internal trace to provide a desired interconnection between the two die.
This invention takes advantage of the metal in the lead frame paddle area to create internal xe2x80x9cinnerxe2x80x9d lead traces (ILTs) for signal routing for die-to-die interconnection in stacked die lead frame packages. The xe2x80x9cinnerxe2x80x9d leads complement the existing xe2x80x9couterxe2x80x9d leads normally associated with lead frame design, which are used to provide electrical connection between the die and peripheral circuitry.
In one set of embodiments, a first die is mounted over the ILTs, such as with die attach paste or adhesive film, and a second die is mounted over the first die, such as with die attach paste or film adhesive. The first die and ILT area are designed such that there must be sufficient separation between the ILT area and the first die to allow wire connection to the ILTs. There must also be sufficient separation between the first and second die to allow wire connection to the bond pads from the first die.
In another set of embodiments, a first die is mounted over one side of the ILTs, and a second die is mounted on the other side of the ILTs, either with the active side (having the bond pads) or the inactive xe2x80x9cbackxe2x80x9d side facing the ILT paddle area. If the second die is mounted with the active side facing the ILT paddle area, there must be sufficient separation between the top of the die the bottom of the ILT paddle area to allow proper wire connection to bond pads on the second die. If the first die is at least the same size as the ILT paddle area, the separation between the first die and the ILTs must be adequate to allow bond wire connection to the ILTs. This set of embodiments also allows a second die with center bond pads to be connected to the first die. The bond pads of the second die, mounted with the active side facing the ILTs, are connected to center portions of the ILTs, while the bond pads of the first die are connected to outer portions of the ILTs to facilitate the desired signal routing.
In other embodiments, the present invention provides additional benefits, such as allowing a larger lower die to be connected to external fingers of a lead frame while allowing the smaller upper die to be connected to ILTs without bond wires crossing each other. The ILT paddle area leads can be designed such that the ILT fingers extend beyond the tips of the external fingers in a interleaved fashion, i.e., the ends of the external fingers are closer to the die than the ends of the ILTs. With this configuration, a larger bottom die mounted on the ILT paddle area can be wire bonded to the external fingers, while a smaller top die mounted over the larger die can be wire bonded to the ILTs without crossing the bond wires of the top and bottom die.
Using conventional wire bonding techniques, the equivalent of a xe2x80x9cviaxe2x80x9d can also be formed. Wire bonds are used to provide the out-of-plane electrical connections between crossing ILT segments of a specific die-to-die signal path. This allows routing of crossed die-to-die signal paths, similar to the way xe2x80x9cviasxe2x80x9d are used in multi-layer laminate substrates. These wire bond xe2x80x9cviasxe2x80x9d also overcome the inherent limitation of one-dimensional, or single metal layer, routing limitations of a lead frame.
The present invention will be more fully understood when taken in light of the following detailed description taken together with the accompanying drawings.